This invention relates generally to microelectronic semiconductor device fabrication and more particularly to a method of improving isolation between active areas in such devices.
The development of semiconductor integrated circuit design has been characterized by a trend toward increasing circuit densities. As the number of devices per chip has increased, various methods and structures have been devised to improve the isolation between devices. One method is to grow insulating oxide regions between devices. However, the oxide tends to spread laterally in direct proportion to the oxide thickness resulting in a barrier having a width substantially equal to its depth, which uses up valuable space on the chip surface. In a typical MOS device the isolating oxide region formed by conventional local oxidation techniques around the device perimeter has a width of about 2.5 microns. If the isolating oxide width were reduced to one micron or less, more than twice the number of circuit elements could be formed in a given chip surface area.
A problem that arises during the fabrication of CMOS devices is the avoidance of latchup, for example, the parasitic lateral npn devices formed by the n+ source and drain diffusions of n-channel devices in the p-type epitaxial layer itself. One solution is to form p+ reachthrough diffusions to the p+ substrate to isolate the n-well, which serve as barriers to minority carriers in the lateral parasitic devices. A desired p+ reachthrough would have, for example, a boron concentration of about 10.sup.18 atoms per cm.sup.3 vertically through the p-type epitaxial layer thickness. This becomes difficult, however, unless excessive diffusion temperatures and times are used, particularly if it is desired to drive in the dopant simultaneously with the n-well diffusions. This is because of the drop in concentration where the downward surface diffusion meets the up-diffusing p+ substrate, resulting in a less effective barrier. Yet another isolation problem in semiconductor fabrication occurs in FET processing, in which local oxidation masking is used during a threshold adjusting implant in the field region to increase the threshold of parasitic devices. During the subsequent growth of thick oxide there is an encroachment of the field implant into the channel area which causes an effective width reduction for electrical conduction in the channel. This encroachment becomes an increasingly significant fraction of the channel width as devices are scaled down to the submicron range of very large scale integration (VLSI). Further, the abuttment of an n+ diffused line against the p+ field implant results in increased depletion capacitance at the sidewall of the diffusion, which can dominate the capacitance of diffused lines.
Accordingly, it is an object of this invention to provide a method of isolating active areas in the fabrication of semiconductor integrated circuits.
Another object of this invention is to provide an isolation structure whose width is independent of its depth.
Still another object of this invention is to provide a method of fabricating semiconductor devices having a substantially increased packing density of circuit elements.